Field
The present disclosure relates generally to electronic apparatus, and more particularly, to method and apparatuses for managing entering or exiting of power-down modes for multiple cores.
Background
A typical electronic apparatus, such as a processor within wireless devices, may include various cores operating within different power domains. A core may vary from a collection of transistors or circuits to an execution unit. Increasingly, the cores may enter or exit power-down modes at various times to manage power consumption. The power-down modes vary and may include a power-collapse mode, in which all power is disconnected from the cores. Other power-down modes may include gating the clocks with the cores (e.g., disabling clocking in the cores). Yet other power-down modes may include adjusting the operating voltages and frequencies of the cores. While the entering and exiting of the power-down modes may conserve power, such changes of power-down modes may lead to various drawbacks. One design challenge is to manage the entering or exiting of the power-down modes for multiple cores and mitigate the drawbacks.